Dynamic random access memory (DRAM) devices are found in a wide range of electronic devices, including computers, smart phones, tablets, game consoles, and televisions. DRAM devices allow the applications running on these electronic devices to temporarily store instructions and data from the non-volatile storage in the device (e.g. FLASH memory or hard drives) before the instructions are executed by the central processing unit (CPU) or other fixed hardware units of the device.
For efficiency reasons, DRAM devices are shared by many different master devices, or intellectual-property (IP) logic blocks that can generate read or write traffic to the DRAM memory devices, in an electronic system. Each master device issues memory requests to the DRAM devices, often via a bus fabric and a memory controller. The memory controller is responsible for scheduling these memory requests and determining how the requests are sent to the DRAM devices. The access latency and, therefore, the effective utilization bandwidth of the DRAM devices depend on how efficiently and effectively the memory controller is able to schedule the requests. When the scheduling is inefficient, excessive bandwidth variations can cause failures in hardware and software applications of the system, such as a frame rate drop in a video game or sound popping due to missing audio frames. A common approach to prevent these failures is to utilize a quality of service (QoS) logic determining how the requests are scheduled and to perform extensive testing to ensure that the application will not fail under as many known bandwidth variation scenarios as possible.
In the prior art, QoS logic solutions primarily relied on two mechanisms: prioritization and rate limiting. A prioritization mechanism favors requests from masters that have been assigned higher priority by the system over requests from masters that have been assigned a lower priority. To prevent the starvation of low priority masters, however, a rate limiting mechanism is used to prevent high priority masters from exceeding an amount of bandwidth allocated to them by the system.
However, these prior QoS logic solutions still allowed for wide variations in the effective bandwidth of the DRAM devices, as perceived by the master devices. As such, software applications developed for electronic systems utilizing prior QoS logic solutions were limited to a specific type of DRAM for which the bandwidth variations has been extensively tested. If a different type of DRAM device, either faster or slower, was used in the system, the QoS logic solution would undergo additional bandwidth variations and the software application would fail to run properly. In the example of game consoles, which typically have long product lifecycles, this drawback prevents console makers from switching to faster, cheaper types of DRAM during a latter period of the lifecycle of a game console for fear that previously developed games will not run properly on the updated hardware.